3/1/2024 0 Comments Cpu transistor size microscope![]() There are cutouts in the oxide layer where the metal layer connects to the circuitry below. (Aside: we left out most of the epitaxial pocket material, because even though we used transparent acrylic to represent it, the layers of the components are much more visible without it present.) We glued most of the layers together, but left the top two layers removable so that it is easier to see the internal structure when the top is removed. It is also fun to imagine what other circuits could have been made with different connections. The unconnected and unused components are easier to see, and provide a visual example that is useful for understanding what the connected components look like under the metal layer. There are also several unused resistors (resistors are the dogbone shapes). There are two unused transistors: one of them is unconnected, and the other is shorted. One of the reasons that this particular chip is educational to look at is that there are a few unused components on the die. The model of the chip die includes a transparent cover representing the oxide layer, and that supports the metal layer with the wire bond pads on the edges. It is removable so that the layers of the model can be more easily inspected. The top layer of this little model has labels for the collector, emitter and base. (Transistors like these are planar: The emitter is above the base, and the base is above the collector.) If you lift it up, and look through the transparent middle layers, you can tell that the emitter (red) is embedded into the top of the base (yellow) and does not go all the down way through it. Working from Eric’s CAD model, we built a single NPN transistor model from layers of colored acrylic. Simultaneously, Ken designed a printed circuit board version for use with discrete components that maintained the same structure as the IC. We’ll be bringing one of these bare chips and a microscope (equipped with both eyepieces and a camera) to Maker Faire.įor the macroscopic scale, we approached visualizing this circuit from a couple of angles: the physical structure of the chip, and the electronic structure of the circuit.Įric Schlaepfer used the die photo to model the structure of the chip in CAD. He made a video about the process - no small feat. John McMaster decapped a few of the chips and sent us a die photo. If you look at the left side, if either of those inputs goes high, the transistor pulls the output low. Here’s the schematic diagram, adapted from the original datasheet. When we push either of the two buttons for one of the gates, that LED will turn off. Ken Shirriff built a circuit with the chip to demonstrate its functionality. Here’s the pinout there are two NOR gates in the chip, plus power and ground. It’s in a funny old “glob-top” can package with eight leads. This chip belongs to the resistor–transistor logic (RTL) family. For this, we picked what turns out to be a rather obscure chip: the Fairchild μL914, which is a dual 2-input NOR gate. To take this to the next level for this year’s Maker Faire, we decided to try and close the loop to take one simple integrated circuit and elucidate its workings well enough that visitors to our booth will be able to see every single component of the circuit, understand their function, and relate it to the macroscopic behavior of the chip. We had a great time helping visitors look at the features and get a glimpse of what’s inside those black box integrated circuit packages. At the 2018 Bay Area Maker Faire, our project Uncovering the Silicon showed off a number of simple and complex integrated circuits (with rather large feature size) under the microscope.
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